1. Field of the Invention
The present invention is directed in general to field of integrated circuit verification. In one aspect, the present invention relates to testing of shadow logic in an integrated circuit.
2. Description of the Related Art
As the complexity and density of integrated circuits increases, the challenges required for testing the circuit also increases, thereby increasing the complexity, time, and costs for the total design effort. For example, integrated circuits increasingly include non-logic structures (e.g., memory blocks, fuses, analog blocks, and/or proprietary design blocks) which are surrounded by shadow logic (e.g., the gates and logic circuits surrounding the non-logic or memory block structures). While industry standard tests, such as built-in self test (BIST) or built-in test (BIT) mechanisms, can be used to test the non-logic structures, such tests do not provide complete test coverage for the shadow logic. In addition, conventional testing mechanisms do not separately test the shadow logic in isolation or independently from the non-logic structures, so instead a built-in test circuit typically tests the non-logic block and ignores the shadow logic. Attempts to separately test the shadow logic by including a scan wrapper around the non-logic structure can degrade performance of the system by increasing the number of access cycles. In the case of integrated circuits incorporating logic and non-logic functions, additional problems may occur when testing shadow logic around programmable non-logic structures. For example, a non-logic block, such as a read only memory, may be programmed in a first state to generate a restricted range of test inputs that can be applied to downstream shadow logic, resulting in undetected defects in the shadow logic that can reduce reliability. To overcome this limitation in case the non-logic block is re-programmed in a second state, scan tests must be regenerated to re-test the shadow logic.